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                                            <a href="/blog/2020-07-05-explanation-of-FPGA-chip-naming-rules/">
                                                关于FPGA芯片命名规则的解释
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                                                    <p>
                                                        发布于：2020年7月5日
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                                                        更新于：2020年7月5日
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                                        <h3 id="Xilinx的FPGA芯片">
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                                            </a>
                                            Xilinx的FPGA芯片
                                        </h3>
                                        <p>
                                            &emsp;&emsp;例如XC7VX485T-2FFG1761C:
                                            <br>
                                            &emsp;&emsp;
                                            <code>
                                                XC7VX485T
                                            </code>
                                            是芯片型号，表示属于Xilinx公司的V7系列的芯片，485T表示其有48.5万个逻辑单元。
                                            <br>
                                            &emsp;&emsp;
                                            <code>
                                                -2
                                            </code>
                                            表示速度等级，对于Xilinx FPGA来说，一般有-1，-2，-3三个等级，值越大，速度越高。
                                            <br>
                                            &emsp;&emsp;
                                            <code>
                                                FFG
                                            </code>
                                            表示封装方式，
                                            <code>
                                                1761
                                            </code>
                                            表示引脚数，
                                            <code>
                                                C
                                            </code>
                                            代表的是温度等级Temperature grade ，这里是商用(Commercial)，如果是
                                            <code>
                                                I
                                            </code>
                                            就是工业用。
                                        </p>
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                                            <a href="/blog/2020-06-24-1-14-tcl-commands/">
                                                1-14-Vivado时序约束中Tcl命令的对象及属性
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                                                    <p>
                                                        发布于：2020年6月24日
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                                                        更新于：2020年6月24日
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                                        <h2 id="Vivado时序约束中Tcl命令的对象及属性">
                                            <a href="#Vivado时序约束中Tcl命令的对象及属性" class="headerlink" title="Vivado时序约束中Tcl命令的对象及属性">
                                            </a>
                                            Vivado时序约束中Tcl命令的对象及属性
                                        </h2>
                                        <p>
                                            &emsp;&emsp;在前面的章节中，我们用了很多Tcl的指令，但有些指令并没有把所有的参数多列出来解释，这一节，我们就把约束中的Tcl指令详细讲一下。
                                        </p>
                                        <p>
                                            我们前面讲到过
                                            <code>
                                                get_pins
                                            </code>
                                            和
                                            <code>
                                                get_ports
                                            </code>
                                            的区别，而且我们也用过
                                            <code>
                                                get_cells
                                            </code>
                                            、
                                            <code>
                                                get_clocks
                                            </code>
                                            和
                                            <code>
                                                get_nets
                                            </code>
                                            这几个指令，下面就通过一张图直观展现它们的区别。
                                        </p>
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                                            <a href="/blog/2020-06-18-1-13-vivado-timing-tools/">
                                                1-13-Vivado时序约束辅助工具
                                            </a>
                                        </h2>
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                                                        voiue
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                                                    <p>
                                                        发布于：2020年6月18日
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                                                        更新于：2020年6月18日
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                                        <h2 id="时序约束辅助工具">
                                            <a href="#时序约束辅助工具" class="headerlink" title="时序约束辅助工具">
                                            </a>
                                            时序约束辅助工具
                                        </h2>
                                        <p>
                                            &emsp;&emsp;上面我们讲的都是xdc文件的方式进行时序约束，Vivado中还提供了两种图形界面的方式，帮我们进行时序约束：时序约束编辑器（Edit
                                            Timing Constraints ）和时序约束向导（Constraints Wizard）。两者都可以在综合或实现后的Design中打开。
                                        </p>
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                                            <a href="/blog/2020-06-16-1-12-multicycle-path/">
                                                1-12-FPGA时序约束实战篇之多周期路径约束
                                            </a>
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                                                        voiue
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                                                        发布于：2020年6月16日
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                                                        更新于：2020年6月16日
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                                        <h3 id="多周期路径约束">
                                            <a href="#多周期路径约束" class="headerlink" title="多周期路径约束">
                                            </a>
                                            多周期路径约束
                                        </h3>
                                        <p>
                                            &emsp;&emsp;多周期路径，我们一般按照以下4个步骤来约束：
                                        </p>
                                        <ol>
                                            <li>
                                                带有使能的数据
                                            </li>
                                        </ol>
                                        <p>
                                            &emsp;&emsp;首先来看带有使能的数据，在本工程中的Tming Report中，也提示了同一个时钟域之间的几个路径建立时间不满足要求
                                        </p>
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                                            <a href="/blog/2020-06-15-1-11-false-path/">
                                                1-11-FPGA时序约束实战篇之伪路径约束
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                                                        voiue
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                                                    <p>
                                                        发布于：2020年6月15日
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                                                        更新于：2020年6月15日
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                                        <h3 id="5-伪路径约束">
                                            <a href="#5-伪路径约束" class="headerlink" title="5. 伪路径约束">
                                            </a>
                                            5. 伪路径约束
                                        </h3>
                                        <p>
                                            &emsp;&emsp;在不加伪路径的时序约束时，Timing Report会提示很多的error，其中就有跨时钟域的error。
                                        </p>
                                    </div>
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                                            <a href="/blog/2020-06-13-1-10-dealy-constraints/">
                                                1-10-FPGA时序约束实战篇之延迟约束
                                            </a>
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                                                        voiue
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                                                    <p>
                                                        发布于：2020年6月13日
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                                                        更新于：2020年6月13日
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                                        <h3 id="延迟约束">
                                            <a href="#延迟约束" class="headerlink" title="延迟约束">
                                            </a>
                                            延迟约束
                                        </h3>
                                        <p>
                                            &emsp;&emsp;对于延迟约束，相信很多同学是不怎么用的，主要可能就是不熟悉这个约束，也有的是嫌麻烦，因为有时还要计算PCB上的走线延迟导致的时间差。而且不加延迟约束，Vivado也只是在Timing
                                            Report中提示warning，并不会导致时序错误，这也会让很多同学误以为这个约束可有可无。
                                        </p>
                                    </div>
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                                            <a href="/blog/2020-06-12-1-9-generated-clock/">
                                                1-9-FPGA时序约束实战篇之衍生时钟约束
                                            </a>
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                                        <hr>
                                    </div>
                                </section>
                                <section class="article typo">
                                    <div class="article-entry" itemprop="articleBody">
                                        <h3 id="约束衍生时钟">
                                            <a href="#约束衍生时钟" class="headerlink" title="约束衍生时钟">
                                            </a>
                                            约束衍生时钟
                                        </h3>
                                        <p>
                                            &emsp;&emsp;系统中有4个衍生时钟，但其中有两个是MMCM输出的，不需要我们手动约束，因此我们只需要对
                                            <code>
                                                clk_samp
                                            </code>
                                            和
                                            <code>
                                                spi_clk
                                            </code>
                                            进行约束即可。约束如下：
                                        </p>
                                        <figure class="highlight plain">
                                            <table>
                                                <tr>
                                                    <td class="gutter">
                                                        <pre>
                                                            <span class="line">
                                                                1
                                                            </span>
                                                            <br>
                                                            <span class="line">
                                                                2
                                                            </span>
                                                            <br>
                                                        </pre>
                                                    </td>
                                                    <td class="code">
                                                        <pre>
                                                            <span class="line">
                                                                create_generated_clock -name clk_samp -source [get_pins clk_gen_i0&#x2F;clk_core_i0&#x2F;clk_tx]
                                                                -divide_by 32 [get_pins clk_gen_i0&#x2F;BUFHCE_clk_samp_i0&#x2F;O]
                                                            </span>
                                                            <br>
                                                            <span class="line">
                                                                create_generated_clock -name spi_clk -source [get_pins dac_spi_i0&#x2F;out_ddr_flop_spi_clk_i0&#x2F;ODDR_inst&#x2F;C]
                                                                -divide_by 1 -invert [get_ports spi_clk_pin]
                                                            </span>
                                                            <br>
                                                        </pre>
                                                    </td>
                                                </tr>
                                            </table>
                                        </figure>
                                    </div>
                                    <!-- <div class="full-width auto-padding tags">
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                                            <a href="/blog/2020-06-10-1-8-primiry-clock/">
                                                1-8-FPGA时序约束实战篇之主时钟约束
                                            </a>
                                        </h2>
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                                <section class="article typo">
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                                        <h3 id="约束主时钟">
                                            <a href="#约束主时钟" class="headerlink" title="约束主时钟">
                                            </a>
                                            约束主时钟
                                        </h3>
                                        <p>
                                            &emsp;&emsp;在这一节开讲之前，我们先把
                                            <code>
                                                wave_gen
                                            </code>
                                            工程的
                                            <code>
                                                wave_gen_timing.xdc
                                            </code>
                                            中的内容都删掉，即先看下在没有任何时序约束的情况下会综合出什么结果？
                                        </p>
                                    </div>
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                                            <a href="#行万里路–时序约束实战篇" class="headerlink" title="行万里路–时序约束实战篇">
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                                            行万里路–时序约束实战篇
                                        </h2>
                                        <p>
                                            &emsp;&emsp;我们以Vivado自带的
                                            <code>
                                                wave_gen
                                            </code>
                                            工程为例，该工程的各个模块功能较为明确，如下图所示。为了引入异步时钟域，我们在此程序上又增加了另一个时钟–
                                            <code>
                                                clkin2
                                            </code>
                                            ，该时钟产生脉冲信号
                                            <code>
                                                pulse
                                            </code>
                                            ，
                                            <code>
                                                samp_gen
                                            </code>
                                            中在
                                            <code>
                                                pulse
                                            </code>
                                            为高时才产生信号。
                                        </p>
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                                            xdc约束优先级
                                        </h3>
                                        <p>
                                            &emsp;&emsp;在xdc文件中，按约束的先后顺序依次被执行，因此，针对同一个时钟的不同约束，只有最后一条约束生效。
                                        </p>
                                        <p>
                                            &emsp;&emsp;虽然执行顺序是从前到后，但优先级却不同；就像四则运算一样，+-x÷都是按照从左到右的顺序执行，但x÷的优先级比+-要高。
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